The present invention relates to an output circuit and, more particularly, to an output circuit for outputting a signal with a high-voltage amplitude.
As an example of an output circuit for an output signal with a high-voltage amplitude, there has been known one which uses a level shift circuit as shown below (see, e.g., Japanese Unexamined Patent Publication No. 2001-223575).
FIG. 5 shows a structure of the conventional output circuit. As shown in FIG. 5, the conventional output circuit comprises an inverter 121 connected between a low-voltage source terminal TVDD and a ground terminal TVSS and driven by an input signal. The conventional output circuit also comprises a latch circuit 123 including an inverter 124 connected between a high-voltage source terminal THVDD and a low-voltage logic terminal THVSS to have an input connected to the output of the inverter 121 via a capacitor 120, and an inverter 125 connected to the output of the latch circuit 123. The output of the inverter 121 and the output of the inverter 125 are each connected to an output circuit 122 connected between the high-voltage source terminal THVDD and the ground terminal TVSS.
The output circuit 122 is composed of a first output transistor MO101 as an N-type MOS (Metal Oxide Semiconductor) transistor and a second output transistor MO102 as a P-type MOS transistor which are connected in this order between the ground terminal TVSS and the high-voltage source terminal THVDD. The connection point between the first output transistor MO101 and the second output transistor MO102 is connected to an output terminal TOUT. The first output transistor MO101 has a gate connected to the output of the inverter 121, while the second output transistor MO102 has a gate connected to the output of the inverter 125.
The potential of the ground terminal TVSS is a ground potential VSS. The potential of the low-voltage source terminal TVDD is VDD. The potential of the high-voltage logic terminal THVDD is HVDD. The potential of the low-voltage logic terminal THVSS is HVSS. The voltage between the low-voltage source terminal TVDD and the ground terminal TVSS and the voltage between the high-voltage source terminal THVDD and the low-voltage logic terminal THVSS are each not more than the gate-source breakdown voltage of each of the transistors composing the circuit. The voltage between the high-voltage source terminal THVDD and the ground terminal TVSS is not less than the gate-source breakdown voltage of each of the transistors.
When an input signal to the input terminal TIN changes to a H level (level VDD), the output of the inverter 121 changes to the L level (level VSS) to turn OFF the first output transistor MO101. The output of the inverter 121 is inputted to the inverter 124 via the capacitor 120. As a result, the input of the inverter 124 changes to the level HVSS and the output of the latch circuit 123 changes to the level HVDD. The change of the output of the latch circuit 123 to the level HVDD brings the output of the inverter 125 to the level HVSS to turn ON the second output transistor MO102. Consequently, the potential of the output terminal TOUT changes to the level HVDD.
On the other hand, when the potential of the input terminal TIN changes to the L level, the output of the inverter 121 changes to the H level to turn ON the first output transistor MO101. The output of the inverter 121 is inputted to the inverter 124 via the capacitor 120. As a result, the input of the inverter 124 changes to the level HVDD and the output of the latch circuit 123 changes to the level HVSS. The change of the output of the latch circuit 123 to the level HVSS brings the output of the inverter 125 to the level HVDD to turn OFF the second output transistor MO102. Consequently, the potential of the output terminal TOUT changes to the level HVSS.
Thus, through the signal transmission by the capacitor 120, it is possible to output a signal with a high-voltage amplitude greater than the amplitude of the gate-source breakdown voltage of each of the transistors composing the circuit.
However, the conventional output circuit described above requires a high-breakdown-voltage capacitor as a capacitor for signal transmission. A process for forming the high-breakdown-voltage capacitor is largely different from a process for forming normal MOS transistors. Consequently, there is the problem of a complicated fabrication process. In addition, to drive an output-stage transistor which has a large gate capacitance, a large drive current becomes necessary so that the capacitor for signal transmission is required to have not only a voltage resistance but also a current capacitance of a given order. This causes the problem that an area occupied by the capacitor for signal transmission increases to prevent a reduction in the size of the output circuit.